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CDCL
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FPGA Accelerated SAT Solver
Keyword:
Boolean SAT
,
FPGA
,
MQP
,
Look Up Table
, and
CDCL
Creator:
Mao, Xinyun
,
David, Samuel
,
Eben, Joshua
, and
Hunter, Patrick
Advisor:
Doroz, Yarkin
and
Mus, Koksal
Publisher:
Worcester Polytechnic Institute
Date Created:
2024-04-25
Resource Type:
Major Qualifying Project
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Major Qualifying Projects
1
Year
2024
1
Creator
David, Samuel
1
Eben, Joshua
1
Hunter, Patrick
1
Mao, Xinyun
1
Advisor
Doroz, Yarkin
1
Mus, Koksal
1
Major
Computer Science
1
Electrical & Computer Engineering
1
Publisher
Worcester Polytechnic Institute
1
Subject
Computing
1
Security
1
Resource type
Major Qualifying Project
1
