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Filtering by: Keyword CDCL Collections Major Qualifying Projects

FPGA Accelerated SAT Solver

Keyword:

Boolean SAT, FPGA, MQP, Look Up Table, and CDCL

Creator:

Mao, Xinyun, David, Samuel, Eben, Joshua, and Hunter, Patrick

Advisor:

Doroz, Yarkin and Mus, Koksal

Publisher:

Worcester Polytechnic Institute

Date Created:

2024-04-25

Resource Type:

Major Qualifying Project